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NXP Semiconductors
LPC1111/12/13/14
5. Block diagram
XTALIN
LPC1111/12/13/14
SWD
XTALOUT
RESET
IRC
CLOCK
GENERATION,
TEST/DEBUG
POWER CONTROL,
CLKOUT
INTERFACE
ARM
CORTEX-M0
POR
SYSTEM
FUNCTIONS
clocks and
controls
system bus
FLASH
8/16/24/32 kB
slave
SRAM
2/4/8 kB
slave
slave
ROM
GPIO ports
PIO0/1/2/3
HIGH-SPEED
GPIO
slave
AHB-LITE BUS
slave
AHB TO APB
BRIDGE
RXD
TX D
DTR, DSR (1) , C TS,
UART
10-bit ADC
AD[7:0]
DCD (1) , RI (1) , RTS
CT32B0_MAT[3:0]
CT32B0_CAP0
CT32B1_MAT[3:0]
CT32B1_CAP0
CT16B0_MAT[2:0]
CT16B0_CAP0
CT16B1_MAT[1:0]
CT16B1_CAP0
32-bit COUNTER/TIMER 0
32-bit COUNTER/TIMER 1
16-bit COUNTER/TIMER 0
16-bit COUNTER/TIMER 1
SPI0
SPI1 (1)
I 2 C-BUS
WDT
SCK0, SSEL0
MISO0, MOSI0
SCK1, SSEL1
MISO1, MOSI1
SCL
SDA
IOCONFIG
SYSTEM CONTROL
PMU
002aae696
(1) LQFP48 and PLCC44 packages only.
Fig 1.
LPC1111/12/13/14 block diagram
LPC1111_12_13_14_0
? NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 00.11 — 13 November 2009
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